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| ltc2482 1 2482fc typical application features applications description 16-bit ? adc with easy drive input current cancellation +fs error vs r source at in + and in C n easy drive ? technology enables rail-to-rail inputs with zero differential input current n directly digitizes high impedance sensors with full accuracy n 600nv rms noise, independent of v ref n operates with a reference as low as 100mv with 16-bit resolution n gnd to v cc input/reference common mode range n simultaneous 50hz/60hz rejection mode n 2ppm inl, no missing codes n 1ppm offset and 15ppm total unadjusted error n no latency: digital filter settles in a single cycle n single supply 2.7v to 5.5v operation n internal oscillator n available in a tiny (3mm 3mm) 10-lead dfn package n direct sensor digitizer n weight scales n direct temperature measurement n strain gauge transducers n instrumentation n industrial process control n dvms and meters the ltc ? 2482 combines a 16-bit plus sign no latency ? ? analog-to-digital converter with patented easy drive technology. the patented sampling scheme eliminates dynamic input current errors and the shortcomings of on- chip buffering through automatic cancellation of differential input current. this allows large external source impedances and input signals with rail-to-rail input range to be directly digitized while maintaining exceptional dc accuracy. the ltc2482 allows a wide common mode input range (0v to v cc ) independent of the reference voltage. the reference can be as low as 100mv or can be tied directly to v cc . the noise level is 600nv rms independent of v ref . this allows direct digitization of low level signals with 16-bit accuracy. the ltc2482 includes an on-chip trimmed oscillator, eliminating the need for external crystals or oscillators and provides 87db rejection of 50hz and 60hz line frequency noise. absolute accuracy and low drift are automatically maintained through continuous, transparent, offset and full-scale calibration. r source () 1 +fs error (ppm) C20 0 20 1k 100k 2482 ta02 C40 C60 C80 10 100 10k 40 60 80 v cc = 5v v ref = 5v v in + = 3.75v v in C = 1.25v f o = gnd t a = 25c c in = 1f ltc2482 v ref v cc v cc gnd f o 1f sdo 3-wire spi interface 0.1f 10k i diff = 0 10k sck 2482 ta01 cs sense v in + v in C 0.1f l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. no latency ? and easy drive are trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
ltc2482 2 2482fc pin configuration absolute maximum ratings (notes 1, 2) top view 11 dd package 10-lead (3mm s 3mm) plastic dfn 10 9 6 7 8 4 5 3 2 1 f o sck gnd sdo cs *gnd v cc v ref in + in ? t jmax = 125c, ja = 160c/w exposed pad (pin #) is gnd, must be soldered to pcb *pin 1 may be driven with a digital signal in order to remain pin compatible with the ltc2480/ltc2482 electrical characteristics (normal speed) the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (notes 3, 4) order information lead free finish tape and reel part marking* package description temperature range ltc2482cdd#pbf ltc2482cdd#trpbf lbsq 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc2482idd#pbf ltc2482idd#trpbf lbsq 10-lead (3mm 3mm) plastic dfn ?40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ supply voltage (v cc ) to gnd ...................... ?0.3v to 6v analog input voltage to gnd ....... ?0.3v to (v cc + 0.3v) reference input voltage to gnd .. ?0.3v to (v cc + 0.3v) digital input voltage to gnd ........ ?0.3v to (v cc + 0.3v) digital output voltage to gnd ...... ?0.3v to (v cc + 0.3v) operating temperature range ltc2482c ............................................... 0c to 70c ltc2482i ............................................ ?40c to 85c storage temperature range .................. ?65c to 125c parameter conditions min typ max units resolution (no missing codes) 0.1 v ref v cc , ?fs v in +fs (note 5) l 16 bits integral nonlinearity 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v (note 6) 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v (note 6) l 2 1 20 ppm of v ref ppm of v ref offset error 2.5v v ref v cc , gnd in + = in ? v cc (note 14) l 0.5 5 v offset error drift 2.5v v ref v cc , gnd in + = in ? v cc 10 nv/c positive full-scale error 2.5v v ref v cc , in + = 0.75v ref , in ? = 0.25v ref l 32 ppm of v ref positive full-scale error drift 2.5v v ref v cc , in + = 0.75v ref , in ? = 0.25v ref 0.1 ppm of v ref /c negative full-scale error 2.5v v ref v cc , in + = 0.75v ref , in ? = 0.25v ref l 32 ppm of v ref negative full-scale error drift 2.5v v ref v cc , in + = 0.75v ref , in ? = 0.25v ref 0.1 ppm of v ref /c total unadjusted error 5v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v 5v v cc 5.5v, v ref = 5v, v in(cm) = 2.5v 2.7v v cc 5.5v, v ref = 2.5v, v in(cm) = 1.25v 15 ppm of v ref ppm of v ref ppm of v ref output noise 5v v cc 5.5v, v ref = 5v, gnd in ? = in + v cc (note 13) 0.6 v rms ltc2482 3 2482fc converter characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (notes 3, 4) parameter conditions min typ max units input common mode rejection dc 2.5v v ref v cc , gnd in C = in + v cc (note 5) l 140 db input common mode rejection, 50hz 2% 2.5v v ref v cc , gnd in C = in + v cc (note 5) l 140 db input common mode rejection, 60hz 2% 2.5v v ref v cc , gnd in C = in + v cc (note 5) l 140 db input normal mode rejection, 50hz 2% 2.5v v ref v cc , gnd in C = in + v cc (notes 5, 7) l 110 120 db input normal mode rejection, 60hz 2% 2.5v v ref v cc , gnd in C = in + v cc (notes 5, 8) l 110 120 db input normal mode rejection, 50hz/60hz 2% 2.5v v ref v cc , gnd in C = in + v cc (notes 5, 9) l 87 db reference common mode rejection dc 2.5v v ref v cc , gnd in C = in + v cc (note 5) l 120 140 db power supply rejection dc v ref = 2.5v, in C = in + = gnd 120 db power supply rejection, 50hz 2% v ref = 2.5v, in C = in + = gnd (note 7) 120 db power supply rejection, 60hz 2% v ref = 2.5v, in C = in + = gnd (note 8) 120 db analog input and reference the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) symbol parameter conditions min typ max units in + absolute/common mode in + voltage gnd C 0.3v v cc + 0.3v v in C absolute/common mode in C voltage gnd C 0.3v v cc + 0.3v v fs full scale of the differential input (in + C in C ) l 0.5v ref v lsb least signi? cant bit of the output code l fs/2 16 v in input differential voltage range (in + C in C ) l Cfs +fs v v ref reference voltage range l 0.1 v cc v c s (in + )in + sampling capacitance 11 pf c s (in C )in C sampling capacitance 11 pf c s (v ref )v ref sampling capacitance 11 pf i dc_leak (in + )in + dc leakage current sleep mode, in + = gnd l C10 1 10 na i dc_leak (in C )in C dc leakage current sleep mode, in C = gnd l C10 1 10 na i dc_leak (v ref )v ref leakage current sleep mode, v ref = v cc l C100 1 100 na ltc2482 4 2482fc digital inputs and digital outputs the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) symbol parameter conditions min typ max units v ih high level input voltage; cs , f o 2.7v v cc 5.5v (note 16) l v cc C 0.5 v v il low level input voltage; cs , f o 2.7v v cc 5.5v l 0.5 v v ih high level input voltage, sck 2.7v v cc 5.5v (note 10) l v cc C 0.5 v v il low level input voltage, sck 2.7v v cc 5.5v (note 10) l 0.5 v i in digital input current; cs , f o 0v v in v cc l C10 10 a i in digital input current, sck 0v v in v cc (note 10) l C10 10 a c in digital input capacitance; cs , f o 10 pf c in digital input capacitance, sck 10 pf v oh high level output voltage, sdo i o = C800a l v cc C 0.5 v v ol low level output voltage, sdo i o = 1.6ma l 0.4 v v oh high level output voltage, sck i o = C800a l v cc C 0.5 v v ol low level output voltage, sck i o = 1.6ma l 0.4 v i oz hi-z output leakage, sdo l C10 10 a power requirements the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) symbol parameter conditions min typ max units v cc supply voltage l 2.7 5.5 v i cc supply current conversion mode (note 12) sleep mode (note 12) l l 160 1 250 2 a a ltc2482 5 2482fc timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) symbol parameter conditions min typ max units f eosc external oscillator frequency range (note 15) l 10 4000 khz t heo external oscillator high period l 0.125 100 s t leo external oscillator low period l 0.125 100 s t conv_1 conversion time simultaneous 50hz/60hz external oscillator l l 144.1 146.9 41036/f eosc (in khz) 149.9 ms ms f isck internal sck frequency internal oscillator (note 10) external oscillator (notes 10, 11) 38.4 f eosc /8 khz khz d isck internal sck duty cycle (note 10) l 45 55 % f esck external sck frequency range (note 10) l 4000 khz t lesck external sck low period (note 10) l 125 ns t hesck external sck high period (note 10) l 125 ns t dout_isck internal sck 24-bit data output time internal oscillator (notes 10, 12) external oscillator (notes 10, 11) l l 0.61 0.625 192/f eosc (in khz) 0.64 ms ms t dout_esck external sck 24-bit data output time (note 10) l 24/f esck (in khz) ms t 1 cs to sdo low l 0 200 ns t 2 cs to sdo hi-z l 0 200 ns t 3 cs to sck? (note 10) l 0 200 ns t 4 cs to sck (note 10) l 50 ns t kqmax sck to sdo valid l 200 ns t kqmin sdo hold after sck (note 5) l 15 ns t 5 sck set-up before cs l 50 ns t 6 sck hold after cs l 50 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd. note 3: v cc = 2.7v to 5.5v unless otherwise speci? ed: v refcm = v ref /2, fs = 0.5v ref v in = in + C in C , v in(cm) = (in + + in C )/2 note 4: use internal conversion clock or external conversion clock source with f eosc = 307.2khz unless otherwise speci? ed. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is de? ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: f eosc = 256khz 2% (external oscillator). note 8: f eosc = 307.2khz 2% (external oscillator). note 9: simultaneous 50hz/60hz rejection (internal oscillator) or f eosc = 280khz 2% (external oscillator). note 10: the sck can be con? gured in external sck mode or internal sck mode. in external sck mode, the sck pin is used as digital input and the driving clock is f esck . in internal sck mode, the sck pin is used as digital output and the output clock signal during the data output is f isck . note 11: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 12: the converter uses the internal oscillator. note 13: the output noise includes the contribution of the internal calibration operations. note 14: guaranteed by design and test correlation. note 15: refer to applications information section for performance vs data rate graphs. note 16: for v cc < 3v, v ih is 2.5v for pin f o . ltc2482 6 2482fc typical performance characteristics integral nonlinearity (v cc = 5v, v ref = 5v) integral nonlinearity (v cc = 5v, v ref = 2.5v) total unadjusted error (v cc = 5v, v ref = 5v) total unadjusted error (v cc = 5v, v ref = 2.5v) total unadjusted error (v cc = 2.7v, v ref = 2.5v) offset error vs v in(cm) offset error vs temperature offset error vs v cc integral nonlinearity (v cc = 2.7v, v ref = 2.5v) input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C1.5 C0.5 0.5 1.5 2482 g01 2.5 C2 C2.5 C1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 85c C45c 25c input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C0.75 C0.25 0.25 0.75 2482 g02 1.25 C1.25 v cc = 5v v ref = 2.5v v in(cm) = 1.25v f o = gnd C45c, 25c, 90c input voltage (v) C3 inl (ppm of v ref ) C1 1 3 C2 0 2 C0.75 C0.25 0.25 0.75 2482 g03 1.25 C1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd C45c, 25c, 90c input voltage (v) C12 tue (ppm of v ref ) C4 4 12 C8 0 8 C1.5 C0.5 0.5 1.5 2482 g04 2.5 C2 C2.5 C1 0 1 2 v cc = 5v v ref = 5v v in(cm) = 2.5v f o = gnd 85c 25c C45c input voltage (v) C12 tue (ppm of v ref ) C4 4 12 C8 0 8 C0.75 C0.25 0.25 0.75 2482 g05 1.25 C1.25 v cc = 5v v ref = 5v v in(cm) = 1.25v f o = gnd 85c 25c C45c input voltage (v) C12 tue (ppm of v ref ) C4 4 12 C8 0 8 C0.75 C0.25 0.25 0.75 2482 g06 1.25 C1.25 v cc = 2.7v v ref = 2.5v v in(cm) = 1.25v f o = gnd 85c 25c C45c v in(cm) (v) C1 offset error (ppm of v ref ) 0.1 0.2 0.3 24 2482 g07 0 C0.1 01 356 C0.2 C0.3 v cc = 5v v ref = 5v v in = 0v t a = 25c temperature (c) C45 C0.3 offset error (ppm of v ref ) C0.2 0 0.1 0.2 C15 15 30 90 2482 g08 C0.1 C30 0 45 60 75 0.3 v cc = 5v v ref = 5v v in = 0v v in(cm) = gnd f o = gnd v cc (v) 2.7 offset error (ppm of v ref ) 0.1 0.2 0.3 3.9 4.7 2482 g09 0 C0.1 3.1 3.5 4.3 5.1 5.5 C0.2 C0.3 ref + = 2.5v ref C = gnd v in = 0v v in(cm) = gnd t a = 25c ltc2482 7 2482fc typical performance characteristics offset error vs v ref on-chip oscillator frequency vs temperature on-chip oscillator frequency vs v cc psrr vs frequency at v cc v ref (v) 0 C0.3 offset error (ppm of v ref ) C0.2 C0.1 0 0.1 0.2 0.3 1234 2482 g10 5 v cc = 5v ref C = gnd v in = 0v v in(cm) = gnd t a = 25c temperature (c) C45 C30 300 frequency (khz) 304 310 C15 30 45 2482 g11 302 308 306 15 0 60 75 90 v cc = 4.1v v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd v cc (v) 2.5 300 frequency (khz) 302 304 306 308 310 3.0 3.5 4.0 4.5 2482 g12 5.0 5.5 v ref = 2.5v v in = 0v v in(cm) = gnd f o = gnd psrr vs frequency at v cc frequency at v cc (hz) 0 0 C20 C40 C60 C80 C100 C120 C140 1k 100k 2482 g13 10 100 10k 1m rejection (db) v cc = 4.1v dc v ref = 2.5v in + = gnd in C = gnd f o = gnd t a = 25c frequency at v cc (hz) 0 C140 rejection (db) C120 C80 C60 C40 0 20 100 140 2482 g14 C100 C20 80 180 220 200 40 60 120 160 v cc = 4.1v dc 1.4v v ref = 2.5v in + = gnd in C = gnd f o = gnd t a = 25c psrr vs frequency at v cc conversion current vs temperature sleep mode current vs temperature conversion current vs data output rate frequency at v cc (hz) 30600 C60 C40 0 30750 2482 g15 C80 C100 30650 30700 30800 C120 C140 C20 rejection (db) v cc = 4.1v dc 0.7v v ref = 2.5v in + = gnd in C = gnd f o = gnd t a = 25c temperature (c) C45 100 conversion current (a) 120 160 180 200 C15 15 30 90 2482 g16 140 C30 0 45 60 75 v cc = 5v v cc = 2.7v f o = gnd cs = gnd sck = nc sdo = nc temperature (c) C45 0 sleep mode current (a) 0.2 0.6 0.8 1.0 2.0 1.4 C15 15 30 90 2482 g17 0.4 1.6 1.8 1.2 C30 0 45 60 75 v cc = 5v v cc = 2.7v f o = gnd cs = v cc sck = nc sdo = nc output data rate (readings/sec) 0 supply current (a) 500 450 400 350 300 250 200 150 100 80 2482 g18 20 40 60 100 70 10 30 50 90 v cc = 5v v cc = 3v v ref = v cc in + = gnd in C = gnd sck = nc sdo = nc cs = gnd f o = ext osc t a = 25c ltc2482 8 2482fc pin functions gnd (pin 1): ground. this pin should be tied to ground; however, in order to remain pin compatible with the ltc2480/ltc2484, this pin may be driven high or low. v cc (pin 2): positive supply voltage. bypass to gnd (pin 8) with a 1f tantalum capacitor in parallel with 0.1f ceramic capacitor as close to the part as possible. v ref (pin 3): positive reference input. the voltage on this pin can have any value between 0.1v and v cc . the negative reference input is gnd (pin 8). in + (pin 4), in C (pin 5): differential analog inputs. the voltage on these pins can have any value between gnd C 0.3v and v cc + 0.3v. within these limits the converter bipolar input range (v in = in + C in C ) extends from C0.5 ? v ref to 0.5 ? v ref . outside this input range the converter produces unique overrange and underrange output codes. cs (pin 6): active low chip select. a low on this pin enables the digital input/output and wakes up the adc. following each conversion the adc automatically enters the sleep mode and remains in this low power state as long as cs is high. a low-to-high transition on cs during the data output transfer aborts the data transfer and starts a new conversion. sdo (pin 7): three-state digital output. during the data output period, this pin is used as the serial data output. when the chip select, cs , is high ( cs = v cc ), the sdo pin is in a high impedance state. during the conversion and sleep periods, this pin is used as the conversion status output. the conversion status can be observed by pulling cs low. gnd (pin 8): ground. shared pin for analog ground, digital ground and reference ground. should be connected directly to a ground plane through a minimum impedance. sck (pin 9): bidirectional digital clock pin. in internal serial clock operation mode, sck is used as the digital output for the internal serial interface clock during the data output period. in external serial clock operation mode, sck is used as the digital input for the external serial interface clock during the data output period. a weak internal pull-up is automatically activated in internal serial clock operation mode. the serial clock operation mode is determined by the logic level applied to the sck pin at power up or during the most recent falling edge of cs . f o (pin 10): frequency control pin. digital input that controls the conversion clock. when f o is connected to gnd the converter uses its internal oscillator running at 307.2khz. the conversion clock may also be overridden by driving the f o pin with an external clock in order to change the output rate or the digital ? lter rejection null. exposed pad (pin 11): this pin is ground and should be soldered to the pcb, gnd plane. for prototyping purposes this pin may remain ? oating. ltc2482 9 2482fc functional block diagram 9 4 5 7 6 10 in + 3 2 v ref v cc f o 8 gnd 1 gnd in C serial interface cs 2482 fd sck sd0 autocalibration and control internal oscillator 3rd order 3 adc ref + in + in C ref C test circuits 1.69k sdo 2482 tc01 hi-z to v oh v ol to v oh v oh to hi-z c load = 20pf 1.69k sdo 2482 tc02 hi-z to v ol v oh to v ol v ol to hi-z c load = 20pf v cc ltc2482 10 2482fc timing diagrams timing diagram using internal sck sdo sck t 1 t 3 sleep t kqmax conversion data out t kqmin t 2 2482 td1 cs timing diagram using external sck sdo sck t 1 t 5 t 6 t 4 sleep t kqmax conversion data out t kqmin t 2 2482 td2 cs applications information converter operation converter operation cycle the ltc2482 is a low power, delta-sigma analog-to-digital converter with an easy-to-use 3-wire serial interface and automatic differential input current cancellation. its opera- tion is made up of three states. the converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see figure 1). the 3-wire interface consists of serial data output (sdo), serial clock (sck) and chip select ( cs ). initially, the ltc2482 performs a conversion. once the conversion is complete, the device enters the sleep state. while in this sleep state, power consumption is reduced convert sleep data output 2482 f01 true false cs = low and sck figure 1. ltc2482 state transition diagram ltc2482 11 2482fc applications information by two orders of magnitude. the part remains in the sleep state as long as cs is high. the conversion result is held inde? nitely in a static shift register while the converter is in the sleep state. once cs is pulled low, the device exits the low power mode and enters the data output state. if cs is pulled high before the ? rst rising edge of sck, the device returns to the low power sleep mode and the conversion result is still held in the internal static shift register. if cs remains low after the ? rst rising edge of sck, the device begins outputting the conversion result. taking cs high at this point will terminate the data output state and start a new conversion. the conversion result is shifted out of the device through the serial data output pin (sdo) on the falling edge of the serial clock (sck) (see figure 2). through timing control of the cs and sck pins, the ltc2482 offers several ? exible modes of operation (internal or external sck and free-running conversion modes). these various modes do not require programming con? guration registers; moreover, they do not disturb the cyclic operation described above. these modes of operation are described in detail in the serial interface timing modes section. easy drive input current cancellation the ltc2482 combines a high precision delta-sigma adc with an automatic differential input current cancellation front end. a proprietary front-end passive sampling net- work transparently removes the differential input current. this enables external rc networks and high impedance sensors to directly interface to the ltc2482 without external ampli? ers. the remaining common mode input current is eliminated by either balancing the differential input impedances or setting the common mode input equal to the common mode reference (see automatic input current cancellation section). this unique architecture does not require on-chip buffers enabling input signals to swing all the way to ground and up to v cc . furthermore, the cancellation does not interfere with the transparent offset and full-scale autocalibration and the absolute ac- curacy (full scale + offset + linearity) is maintained with external rc networks. output data format the ltc2482 serial output data stream is 24 bits long. the ? rst 3 bits represent status information indicating the sign and conversion state. the next 17 bits are the conversion result, msb ? rst. the remaining 4 bits are always zero. bit 21 and bit 20 together are also used to indicate an underrange condition (the differential input voltage is below Cfs) or an overrange condition (the differential input voltage is above +fs). in applications where a processor generates 32 clock cycles, or to remain compatible with higher resolution converters, the ltc2482s digital interface will ignore extra clock edges seen during the next conversion period after the 24th and output 1 for the extra clock cycles. furthermore, cs may be pulled high prior to outputting all 24 bits, aborting the data out transfer and initiating a new conversion. cs sdo hi-z sig bit 21 bit 20 bit 19 bit 18 bit 4 bit 3 bit 2 bit 1 bit 0 bit 22 bit 23 dmy msb b16 conversion result lsb sck sleep data output eoc conversion 2482 f02 figure 2. output data timing ltc2482 12 2482fc applications information bit 23 (? rst output bit) is the end of conversion ( eoc ) indicator. this bit is available at the sdo pin during the conversion and sleep states whenever the cs pin is low. this bit is high during the conversion and goes low when the conversion is complete. bit 22 (second output bit) is a dummy bit (dmy) and is always low. bit 21 (third output bit) is the conversion result sign indicator (sig). if v in is >0, this bit is high. if v in is <0, this bit is low. bit 20 (fourth output bit) is the most signi? cant bit (msb) of the result. this bit in conjunction with bit 21 also provides the underrange or overrange indication. if both bit 21 and bit 20 are high, the differential input voltage is above +fs. if both bit 21 and bit 20 are low, the differential input voltage is below Cfs. the function of these bits is summarized in table 1. table 1. ltc2482 status bits input range bit 23 eoc bit 22 dmy bit 21 sig bit 20 msb v in 0.5 ? v ref 0011 0v v in < 0.5 ? v ref 0010 C0.5 ? v ref v in < 0v 0001 v in < C0.5 ? v ref 0000 bits 20-4 are the 16-bit plus sign conversion result msb ? rst. bits 3-0 are always low and are included to maintain software compatibility with the ltc2480. data is shifted out of the sdo pin under control of the serial clock (sck) (see figure 2). whenever cs is high, sdo remains high impedance and any externally gener- ated sck clock pulses are ignored by the internal data out shift register. in order to shift the conversion result out of the device, cs must ? rst be driven low. eoc is seen at the sdo pin of the device once cs is pulled low. eoc changes in real time from high to low at the completion of a conversion. this signal may be used as an interrupt for an external microcontroller. bit 23 ( eoc ) can be captured on the ? rst rising edge of sck. bit 22 is shifted out of the device on the ? rst falling edge of sck. the ? nal data bit (bit 0) is shifted out on the falling edge of the 23rd sck and may be latched on the rising edge of the 24th sck pulse. on the falling edge of the 24th sck pulse, sdo goes high indicating the initiation of a new conversion cycle. this bit serves as eoc (bit 23) for the next conversion cycle. table 2 summarizes the output data format. as long as the voltage on the in + and in C pins is main- tained within the C0.3v to (v cc + 0.3v) absolute maximum operating range, a conversion result is generated for any differential input voltage v in from Cfs = C0.5 ? v ref to +fs = 0.5 ? v ref . for differential input voltages greater than +fs, the conversion result is clamped to the value corresponding to the +fs + 1lsb. for differential input voltages below Cfs, the conversion result is clamped to the value corresponding to Cfs C 1lsb. table 2. ltc2482 output data format differential input voltage v in * bit 23 eoc bit 22 dmy bit 21 sig bit 20 msb bit 19 bit 18 bit 17 bit 4 bits 3-0 v in * fs** 001100000 fs** C 1lsb 001011110 0.5 ? fs** 001010000 0.5 ? fs** C 1lsb 001001110 0 001000000 C1lsb 000111110 C0.5 ? fs** 000110000 C0.5 ? fs** C 1lsb 000101110 Cfs** 000100000 v in * < Cfs** 000011110 *the differential input voltage v in = in + C in C . **the full-scale voltage fs = 0.5 ? v ref . ltc2482 13 2482fc applications information conversion clock a major advantage the delta-sigma converter offers over conventional type converters is an on-chip digital ? lter (commonly implemented as a sinc or comb ? lter). for high resolution, low frequency applications, this ? lter is typically designed to reject line frequencies of 50hz or 60hz plus their harmonics. the ? lter rejection performance is directly related to the accuracy of the converter system clock. the ltc2482 incorporates a highly accurate on-chip oscillator. this eliminates the need for external frequency setting components such as crystals or oscillators. frequency rejection selection (f o ) the ltc2482 internal oscillator provides better than 87db normal mode rejection at the line frequency and all its harmonics (up to the 255th) for the frequency range 48hz to 62.4hz. when a fundamental rejection frequency different from 50hz/ 60hz is required, when more than 87db rejection is needed for 50hz/60hz, or when the converter must be synchronized with an outside source, the ltc2482 can operate with an external conversion clock. the converter automatically detects the presence of an external clock signal at the f o pin and turns off the internal oscillator. the frequency f eosc of the external signal must be at least 10khz to be detected. the external clock signal duty cycle is not signi? cant as long as the minimum and maximum speci? cations for the high and low periods t heo and t leo are observed. while operating with an external conversion clock of a frequency f eosc , the ltc2482 provides better than 110db normal mode rejection in a frequency range of f eosc /5120 4% and its harmonics. the normal mode rejection as a differential input signal frequency deviation from notch frequency f eosc /5120(%) C12 C8 C4 0 4 8 12 normal mode rejection (db) 2480 f03 C80 C85 C90 C95 C100 C105 C110 C115 C120 C125 C130 C135 C140 figure 3. ltc2482 normal mode rejection when using an external oscillator function of the input frequency deviation from f eosc /5120 is shown in figure 3. whenever an external clock is not present at the f o pin, the converter automatically activates its internal oscillator and enters the internal conversion clock mode. the ltc2482 operation will not be disturbed if the change of conversion clock source occurs during the sleep state or during the data output state while the converter uses an external serial clock. if the change occurs during the conversion state, the result of the conversion in progress may be outside speci? cations but the following conversions will not be affected. if the change occurs during the data output state and the converter is in the internal sck mode, the serial clock duty cycle may be affected but the serial data stream will remain valid. table 3 summarizes the duration of each state and the achievable output data rate as a function of f o . table 3. ltc2482 state duration state operating mode duration convert internal oscillator 50hz/60hz rejection 147ms, output data rate 6.8 readings/s external oscillator f o = external oscillator with frequency f eosc khz (f eosc /5120 rejection) 41036/f eosc s, output data rate f eosc /41036 readings/s sleep as long as cs = high, after a conversion is complete data output internal serial clock f o = low/high (internal oscillator) as long as cs = low but not longer than 0.62ms (24 sck cycles) f o = external oscillator with frequency f eosc khz as long as cs = low but not longer than 192/f eosc ms (24 sck cycles) external serial clock with frequency f sck khz as long as cs = low but not longer than 24/f sck ms (24 sck cycles) ltc2482 14 2482fc applications information ease of use the ltc2482 data output has no latency, ? lter settling delay or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog voltages is easy. the ltc2482 performs offset and full-scale calibrations every conversion cycle. this calibration is transparent to the user and has no effect on the cyclic operation described above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. power-up sequence the ltc2482 automatically enters an internal reset state when the power supply voltage v cc drops below approximately 2v. this feature guarantees the integrity of the conversion result and of the serial interface mode selection. (see the 2-wire i/o sections in the serial interface timing modes section.) when the v cc voltage rises above this critical threshold, the converter creates an internal power-on-reset (por) signal with a duration of approximately 4ms. the por signal clears all internal registers. following the por signal, the ltc2482 starts a normal conversion cycle and follows the succession of states described in figure 1. the ? rst conversion result following por is accurate within the speci? cations of the device if the power supply voltage is restored within the operating range (2.7v to 5.5v) before the end of the por time interval. reference voltage range the ltc2482 external reference voltage range is 0.1v to v cc . the converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in nanovolts is nearly constant with reference voltage. since the transition noise (600nv) is much less than the quantization noise (v ref /217), a decrease in the reference voltage will increase the converter resolution. a reduced reference voltage will improve the converter performance when operated with an external conversion clock (external f o signal) at substantially higher output data rates (see the output data rate section). the negative reference input to the converter is internally tied to gnd. gnd (pin 8) should be connected to a ground plane through as short a trace as possible to minimize volt- age drop. the ltc2482 has an average operational current of 160a and for 1 parasitic resistance, the voltage drop of 160v causes a gain error of 2lsb for v ref = 5v. input voltage range the analog input is truly differential with an absolute/com- mon mode range for the in + and in C input pins extending from gnd C 0.3v to v cc + 0.3v. outside these limits, the esd protection devices begin to turn on and the errors due to input leakage current increase rapidly. within these limits, the ltc2482 converts bipolar differential input signal, v in = in + C in C , from Cfs to +fs where fs = 0.5 ? v ref . outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. since the differential input current cancellation does not rely on an on-chip buffer, current cancellation as well as dc performance is maintained rail-to-rail. input signals applied to in + and in C pins may extend by 300mv below ground and above v cc . in order to limit any fault current, resistors of up to 5k may be added in series with the in + and in C pins without affecting the performance of the devices. the effect of the series resistance on the converter accuracy can be evaluated from the curves presented in the input current/reference current sections. in addition, series resistors will introduce a temperature dependent offset error due to the input leakage current. a 1na input leakage current will develop a 1ppm offset error on a 5k resistor if v ref = 5v. this error has a very strong temperature dependency. ltc2482 15 2482fc applications information serial interface timing modes the ltc2482s 3-wire interface is spi and microwire compatible. this interface offers several ? exible modes of operation. these include internal/external serial clock, 2- or 3-wire i/o, single cycle or continuous conversion. the following sections describe each of these serial interface timing modes in detail. in all these cases, the converter can use the internal oscillator (f o = low or f o = high) or an external oscillator connected to the f o pin. refer to table 4 for a summary. external serial clock, single cycle operation (spi/microwire compatible) this timing mode uses an external serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 4. the serial clock mode is selected on the falling edge of cs . to select the external serial clock mode, the serial clock pin (sck) must be low during each cs falling edge. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. while cs is pulled low, eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. independent of cs , the device automatically enters the low power sleep state once the conversion is complete. when the device is in the sleep state, its conversion re- sult is held in an internal static shift register. the device remains in the sleep state until the ? rst rising edge of sck is seen while cs is low. the output data is shifted out of the sdo pin on each falling edge of sck. this enables external circuitry to latch the output on the rising edge of sck. eoc can be latched on the ? rst rising edge of sck and the last bit of the conversion result can be latched on the 24th rising edge of sck. on the 24th falling edge of sck, the device begins a new conversion. sdo goes high ( eoc = 1) indicating a conversion is in progress. in applications where the processor generates 32 clock cycles, or to remain compatible with higher resolution converters, the ltc2482s digital interface will ignore extra clock edges seen during the next conversion period after the 24th and outputs 1 for the extra clock cycles. at the conclusion of the data cycle, cs may remain low and eoc monitored as an end-of-conversion interrupt. alternatively, cs may be driven high setting sdo to hi-z. as described above, cs may be pulled low at any time in order to monitor the conversion status. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the ? rst rising edge and the 24th falling edge of sck (see figure 5). on the rising edge of cs , the device aborts the data output state and immediately initiates a new conversion. this is useful for systems not requiring all 24 bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. table 4. ltc2482 interface timing modes configuration sck source conversion cycle control data output control connection and waveforms external sck, single cycle conversion external cs and sck cs and sck figures 4, 5 external sck, 2-wire i/o external sck sck figure 6 internal sck, single cycle conversion internal cs cs figures 7, 8 internal sck, 2-wire i/o, continuous conversion internal continuous internal figure 9 ltc2482 16 2482fc applications information eoc bit 23 sdo sck (external) cs test eoc msb sig bit 0 lsb bit 4 bit 19 bit 18 bit 17 bit 16 bit 20 bit 21 bit 22 sleep sleep data output conversion 2482 f04 conversion hi-z hi-z hi-z test eoc v cc f o v ref in + in C sck sdo cs gnd 210 int/ext clock 3 4 5 9 7 8,1 6 reference voltage 0.1v to v cc analog input 1f 2.7v to 5.5v ltc2482 3-wire spi interface test eoc (optional) sdo sck (external) cs data output conversion sleep sleep sleep test eoc data output hi-z hi-z hi-z conversion 2482 f05 msb sig bit 8 bit 19 bit 18 bit 17 bit 16 bit 9 bit 20 bit 21 bit 22 eoc bit 23 bit 0 eoc hi-z test eoc test eoc (optional) v cc f o v ref in + in C sck sdo cs gnd 210 int/ext clock 3 4 5 9 7 8,1 6 reference voltage 0.1v to v cc analog input 1f 2.7v to 5.5v ltc2482 3-wire spi interface figure 4. external serial clock, single cycle operation figure 5. external serial clock, reduced data output length ltc2482 17 2482fc applications information external serial clock, 2-wire i/o this timing mode utilizes a 2-wire serial i/o interface. the conversion result is shifted out of the device by an externally generated serial clock (sck) signal (see figure 6). cs may be permanently tied to ground, simplifying the user interface or transmission over an isolation barrier. the external serial clock mode is selected at the end of the power-on reset (por) cycle. the por cycle is concluded typically 4ms after v cc exceeds approximately 2v. the level applied to sck at this time determines if sck is internal or external. sck must be driven low prior to the end of por in order to enter the external serial clock timing mode. since cs is tied low, the end-of-conversion ( eoc ) can be continuously monitored at the sdo pin during the con- vert and sleep states. eoc may be used as an interrupt to an external controller indicating the conversion result is ready. eoc = 1 while the conversion is in progress and eoc = 0 once the conversion ends. on the falling edge of eoc , the conversion result is loaded into an internal static shift register. the output data is shifted out of the sdo pin on each falling edge of sck. eoc can be latched on the ? rst rising edge of sck. on the 24th falling edge of sck, sdo goes high ( eoc = 1) indicating a new conversion has begun. in applications where the processor generates 32 clock cycles, or to remain compatible with higher resolution converters, the ltc2482s digital interface will ignore extra clock edges seen during the next conversion period after the 24th and outputs 1 for the extra clock cycles. internal serial clock, single cycle operation this timing mode uses an internal serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle (see figure 7). in order to select the internal serial clock timing mode, the serial clock pin (sck) must be ? oating (hi-z) or pulled high prior to the falling edge of cs . the device will not enter the internal serial clock mode if sck is driven low on the falling edge of cs . an internal weak pull-up resistor is active on the sck pin during the falling edge of cs ; therefore, the internal serial clock timing mode is automatically selected if sck is not externally driven. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. once cs is pulled low, sck goes low and eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. eoc bit 23 sdo sck (external) cs msb sig lsb bit 4 bit 19 bit 18 bit 17 bit 16 bit 20 bit 21 bit 22 data output conversion 2482 f06 conversion v cc f o v ref in + in C sck sdo cs gnd 210 int/ext clock 3 4 5 9 7 8,1 6 reference voltage 0.1v to v cc analog input 1f 2.7v to 5.5v ltc2482 2-wire spi interface figure 6. external serial clock, cs = 0 operation ltc2482 18 2482fc applications information when testing eoc , if the conversion is complete ( eoc = 0), the device will exit the low power mode during the eoc test. in order to allow the device to return to the low power sleep state, cs must be pulled high before the ? rst rising edge of sck. in the internal sck timing mode, sck goes high and the device begins outputting data at time t eoctest after the falling edge of cs (if eoc = 0) or t eoctest after eoc goes low (if cs is low during the falling edge of eoc ). the value of t eoctest is 12s if the device is using its internal oscillator. if f o is driven by an external oscillator of frequency f eosc , then t eoctest is 3.6/f eosc in seconds. if cs is pulled high before time t eoctest , the device returns to the sleep state and the conversion result is held in the internal static shift register. if cs remains low longer than t eoctest , the ? rst rising edge of sck will occur and the conversion result is serially shifted out of the sdo pin. the data i/o cycle concludes after the 24th rising edge. the output data is shifted out of the sdo pin on each falling edge of sck. the internally generated serial clock is output to the sck pin. this signal may be used to shift the conversion result into external circuitry. eoc can be latched on the ? rst rising edge of sck and the last bit of the conversion result on the 24th rising edge of sck. after the 24th rising edge, sdo goes high ( eoc = 1), sck stays high and a new conversion starts. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the ? rst and 24th rising edge of sck (see figure 8). on the rising edge of cs , the device aborts the data output state and immediately initiates a new conversion. this is useful for systems not requiring all 24 bits of output data, aborting an invalid conversion cycle, or synchronizing the start of a conversion. if cs is pulled high while the converter is driving sck low, the internal pull-up is not available to restore sck to a logic high state. this will cause the device to exit the internal serial clock mode on the next falling edge of cs . this can be avoided by adding an external 10k pull-up resistor to the sck pin or by never pulling cs high when sck is low. whenever sck is low, the ltc2482s internal pull-up at pin sck is disabled. normally, sck is not externally driven if the device is in the internal sck timing mode. however, certain applications may require an external driver on sck. if this driver goes hi-z after outputting a low signal, the ltc2482s internal pull-up remains disabled. hence, sck remains low. on the next falling edge of cs , the device is switched to the external sck timing mode. by adding an external 10k pull-up resistor to sck, this pin goes high once the external driver goes hi-z. on the next cs falling edge, the device will remain in the internal sck timing mode. sdo sck (internal) cs msb sig bit 0 lsb bit 4 test eoc bit 19 bit 18 bit 17 bit 16 bit 20 bit 21 bit 22 eoc bit 23 sleep sleep data output conversion conversion 2482 f07 ltc2482 21 2482fc applications information an alternate solution is to reduce the edge rate of the control signals. it should be noted that using very slow edges will increase the converter power supply current during the transition time. the differential input architecture reduces the converters sensitivity to ground currents. particular attention must be given to the connection of the f o signal when the ltc2482 is used with an external conversion clock. this clock is active during the conver- sion time and the normal mode rejection provided by the internal digital ? lter is not very high at this frequency. a normal mode signal of this frequency at the converter reference terminals can result in dc gain and inl errors. a normal mode signal of this frequency at the converter input terminals can result in a dc offset error. such pertur- bations can occur due to asymmetric capacitive coupling between the f o signal trace and the converter input and/or reference connection traces. an immediate solution is to maintain maximum possible separation between the f o signal trace and the input/reference signals. when the f o signal is parallel terminated near the converter, substantial ac current is ? owing in the loop formed by the f o con- nection trace, the termination and the ground return path. thus, perturbation signals may be inductively coupled into the converter input and/or reference. in this situation, the user must reduce to a minimum the loop area for the f o signal as well as the loop area for the differential input and reference connections. even when f 0 is not driven, other nearby signals pose similar emi threats which will be minimized by following good layout practices. driving the input and reference the input and reference pins of the ltc2482 converter are directly connected to a network of sampling capaci- tors. depending upon the relation between the differential input voltage and the differential reference voltage, these capacitors are switching between these four pins transfer- ring small amounts of charge in the process. a simpli? ed equivalent circuit is shown in figure 10. for a simple approximation, the source impedance r s driving an analog input pin (in + , in C , v ref + or gnd) can be considered to form, together with r sw and c eq (see figure 10), a ? rst order passive network with a time constant = (r s + r sw ) ? c eq . the converter is able to sample the input signal with better than 1ppm accuracy if the sampling period is at least 14 times greater than the input circuit time constant . the sampling process on the four input analog pins is quasi-independent so each time constant should be considered by itself and, under worst-case circumstances, the errors may add. v ref + v in + v cc r sw (typ) 10k i leak i leak v cc i leak i leak v cc r sw (typ) 10k c eq 12pf (typ) r sw (typ) 10k i leak i in + v in C i in C i ref + i ref C 2482 f10 i leak v cc i leak i leak switching frequency f sw = 123khz internal oscillator f sw = 0.4 ? f eosc external oscillator gnd r sw (typ) 10k figure 10. ltc2482 equivalent analog input current ltc2482 22 2482fc applications information when using the internal oscillator, the ltc2482s front-end switched-capacitor network is clocked at 123khz corre- sponding to an 8.1s sampling period. thus, for settling errors of less than 1ppm, the driving source impedance should be chosen such that 8.1s/14 = 580ns. when an external oscillator of frequency f eosc is used, the sampling period is 2.5/f eosc and, for a settling error of less than 1ppm, 0.178/f eosc . automatic differential input current cancellation in applications where the sensor output impedance is low (up to 10k with no external bypass capacitor or up to 500 with 0.001f bypass), complete settling of the input occurs. in this case, no errors are introduced and direct digitization of the sensor is possible. for many applications, the sensor output impedance combined with external bypass capacitors produces rc time constants much greater than the 580ns required for 1ppm accuracy. for example, a 10k bridge driving a 0.1f bypass capacitor has a time constant an order of magnitude greater than the required maximum. historically, settling issues were solved using buffers. these buffers led to increased noise, reduced dc performance (offset/drift), limited input/output swing (cannot digitize signals near ground or v cc ), added system cost and increased power. the ltc2482 uses a proprietary switching algorithm that forces the average differential input current to zero indepen- dent of external settling errors. this allows accurate direct digitization of high impedance sensors without the need for buffers. additional errors resulting from mismatched leakage currents must also be taken into account. the switching algorithm forces the average input current on the positive input (i in + ) to be equal to the average input current on the negative input (i in C ). over the complete conversion cycle, the average differential input current (i in + C i in C ) is zero. while the differential input current is zero, the common mode input current (i in + + i in C )/2 is proportional to the difference between the common mode input voltage (v incm ) and the common mode reference voltage (v refcm ). in applications where the input common mode voltage is equal to the reference common mode voltage, as in the case of a balance bridge type application, both the differential and common mode input current are zero. the accuracy of the converter is unaffected by settling errors. mismatches in source impedances between in + and in C also do not affect the accuracy. in applications where the input common mode voltage is constant but different from the reference common mode voltage, the differential input current remains zero while the common mode input current is proportional to the differ- ence between v incm and v refcm . for a reference common mode of 2.5v and an input common mode of 1.5v, the common mode input current is approximately 0.74a. this common mode input current has no effect on the accuracy if the external source impedances tied to in + and in C are matched. mismatches in these source impedances lead to a ? xed offset error but do not affect the linearity or full-scale reading. a 1% mismatch in 1k source resistances leads to a 1lsb shift (74v) in offset voltage. in applications where the common mode input voltage varies as a function of input signal level (single-ended input, rtds, half bridges, current sensors, etc.), the com- mon mode input current varies proportionally with input voltage. for the case of balanced input impedances, the common mode input current effects are rejected by the large cmrr of the ltc2482 leading to little degradation in accuracy. mismatches in source impedances lead to gain errors proportional to the difference between the common mode input voltage and the common mode ref- erence voltage. 1% mismatches in 1k source resistances lead to gain worst-case gain errors on the order of 1lsb (for 1v differences in reference and input common mode voltage). table 5 summarizes the effects of mismatched source impedance and differences in reference/input common mode voltages. table 5. suggested input con? guration for ltc2482 balanced input resistances unbalanced input resistances constant v in(cm) C v ref(cm) c in > 1nf at both in + and in C . can take large source resistance with negligible error c in > 1nf at both in + and in C . can take large source resistance. unbalanced resistance results in an offset which can be calibrated varying v in(cm) C v ref(cm) c in > 1nf at both in + and in C . can take large source resistance with negligible error minimize in + and in C capacitors and avoid large source impedance (<5k recommended) ltc2482 23 2482fc applications information the magnitude of the dynamic input current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. the accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. such a speci? cation can also be easily achieved by an external clock. when relatively stable resistors (50ppm/c) are used for the external source impedance seen by in + and in C , the expected drift of the dynamic current and offset will be insigni? cant (about 1% of their respective values over the entire temperature and voltage range). even for the most stringent applications, a one-time calibration operation may be suf? cient. in addition to the input sampling charge, the input esd protection diodes have a temperature dependent leakage current. this current, nominally 1na (10na max), results in a small offset shift. a 1k source resistance will create a 1v typical and 10v maximum offset voltage. reference current in a similar fashion, the ltc2482 samples the differential reference pins v ref + and gnd transferring small amount of charge to and from the external driving circuits thus producing a dynamic reference current. this current does not change the converter offset, but it may degrade the gain and inl performance. the effect of this current can be analyzed in two distinct situations. for relatively small values of the external reference capaci- tors (c ref < 1nf), the voltage on the sampling capacitor settles almost completely and relatively large values for the source impedance result in only small errors. such values for c ref will deteriorate the converter offset and gain performance without signi? cant bene? ts of reference ? ltering and the user is advised to avoid them. larger values of reference capacitors (c ref > 1nf) may be required as reference ? lters in certain con? gurations. such capacitors will average the reference sampling charge and the external source resistance will see a quasi constant reference differential impedance. in the following discussion, it is assumed the input and reference common mode are the same. using internal oscillator (50hz/60hz rejection), the differential reference c in 2482 f11 v incm + 0.5v in r source in + ltc2482 c par 20pf c in v incm C 0.5v in r source in C c par 20pf figure 11. an rc network at in + and in C r source () 1 +fs error (ppm) C20 0 20 1k 100k 2482 f12 C40 C60 C80 10 100 10k 40 60 80 v cc = 5v v ref = 5v v in + = 3.75v v in C = 1.25v f o = gnd t a = 25c c in = 0pf c in = 100pf c in = 1nf, 0.1f, 1f figure 12. +fs error vs r source at in + and in C r source () 1 Cfs error (ppm) C20 0 20 1k 100k 2482 f13 C40 C60 C80 10 100 10k 40 60 80 v cc = 5v v ref = 5v v in + = 1.25v v in C = 3.75v f o = gnd t a = 25c c in = 0pf c in = 100pf c in = 1nf, 0.1f, 1f figure 13. Cfs error vs r source at in + and in C ltc2482 24 2482fc applications information resistance is 1.1m and the resulting full-scale error is 0.46ppm for each ohm of source resistance driving the v ref pin. when f o is driven by an external oscillator with a frequency f eosc (external conversion clock operation), the typical differential reference resistance is 0.33 ? 1012/ f eosc and each ohm of source resistance driving the v ref pin will result in 1.53 ? 10C6 ? f eosc ppm gain error. the typ- ical +fs and Cfs errors for various combinations of source resistance seen by the v ref pin and external capacitance connected to that pin are shown in figures 14-17. in addition to this gain error, the converter inl performance is degraded by the reference source impedance. the inl is caused by the input dependent terms Cv in2 /(v ref ? r eq ) C (0.5 ? v ref ? d t )/r eq in the reference pin current as expressed in figure 10. when using internal oscillator with 50hz/60hz rejection, every 100 of reference source resistance translates into about 0.61ppm additional inl error. when f o is driven by an external oscillator with a frequency f eosc , every 100 of source resistance driving v ref translates into about 1.99 ? 10 C6 ? f eosc ppm addi- tional inl error. figure 18 shows the typical inl error due to the source resistance driving the v ref pin when large c ref values are used. the user is advised to minimize the source impedance driving the v ref pin. r source () 0 +fs error (ppm) 50 70 90 10k 2482 f14 30 10 40 60 80 20 0 C10 10 100 1k 100k v cc = 5v v ref = 5v v in + = 3.75v v in C = 1.25v f o = gnd t a = 25c c ref = 0.01f c ref = 0.001f c ref = 100pf c ref = 0pf r source () 0 Cfs error (ppm) C30 C10 10 10k 2482 f15 C50 C70 C40 C20 0 C60 C80 C90 10 100 1k 100k v cc = 5v v ref = 5v v in + = 1.25v v in C = 3.75v f o = gnd t a = 25c c ref = 0.01f c ref = 0.001f c ref = 100pf c ref = 0pf figure 14. +fs error vs r source at v ref (small c ref ) figure 15. Cfs error vs r source at v ref (small c ref ) r source () 0 +fs error (ppm) 300 400 500 800 2482 f16 200 100 0 200 400 600 1000 v cc = 5v v ref = 5v v in + = 3.75v v in C = 1.25v f o = gnd t a = 25c c ref = 1f, 10f c ref = 0.1f c ref = 0.01f r source () 0 Cfs error (ppm) C200 C100 0 800 2482 f17 C300 C400 C500 200 400 600 1000 v cc = 5v v ref = 5v v in + = 1.25v v in C = 3.75v f o = gnd t a = 25c c ref = 1f, 10f c ref = 0.1f c ref = 0.01f figure 16. +fs error vs r source at v ref (large c ref ) figure 17. Cfs error vs r source at v ref (large c ref ) ltc2482 25 2482fc applications information in applications where the reference and input common mode voltages are different, extra errors are introduced. for every 1v of the reference and input common mode volt- age difference (v refcm C v incm ) and a 5v reference, each ohm of reference source resistance introduces an extra (v refcm C v incm )/(v ref ? r eq ) full-scale gain error which is 0.067ppm when using the internal oscillator (50hz/60hz rejection). if an external clock is used, the corresponding extra gain error is 0.22 ? 10 C6 ? f eosc ppm. the magnitude of the dynamic reference current depends upon the size of the very stable internal sampling capacitors and upon the accuracy of the converter sampling clock. the accuracy of the internal clock over the entire temperature and power supply range is typically better than 0.5%. such a speci? cation can also be easily achieved by an external clock. when relatively stable resistors (50ppm/c) are used for the external source impedance seen by v ref + and gnd, the expected drift of the dynamic current gain error will be insigni? cant (about 1% of its value over the entire temperature and voltage range). even for the most stringent applications a one-time calibration operation may be suf? cient. in addition to the reference sampling charge, the reference pins esd protection diodes have a temperature dependent leakage current. this leakage current, nominally 1na (10na max), results in a small gain error. a 100 source resistance will create a 0.05v typical and 0.5v maximum full-scale error. output data rate when using its internal oscillator, the ltc2482 produces 6.8ps with a notch frequency of 55hz, for simultaneous 50hz/60hz rejection. the actual output data rate will de- pend upon the length of the sleep and data output phases which are controlled by the user and which can be made insigni? cantly short. when operated with an external conversion clock (f o connected to an external oscillator), the ltc2482 output data rate can be increased as desired. the duration of the conversion phase is 41036/f eosc . an increase in f eosc over the nominal 307.2khz will translate into a proportional increase in the maximum output data rate. the increase in output rate is neverthe- less accompanied by three potential effects, which must be carefully considered. first, a change in f eosc will result in a proportional change in the internal notch position and in a reduction of the converter differential mode rejection at the power line fre- quency. in many applications, the subsequent performance degradation can be substantially reduced by relying upon the ltc2482s exceptional common mode rejection and by carefully eliminating common mode to differential mode conversion sources in the input circuit. the user should avoid single-ended input ? lters and should maintain a very high degree of matching and symmetry in the circuits driving the in + and in C pins. second, the increase in clock frequency will increase proportionally the amount of sampling charge transferred through the input and the reference pins. if large external input and/or reference capacitors (c in , c ref ) are used, the previous section provides formulae for evaluating the effect of the source resistance upon the converter performance for any value of f eosc . if small external input and/or reference capacitors (c in , c ref ) are used, the effect of the external source resistance upon the ltc2482 typical performance can be inferred from figures 12, 13, 14 and 15 in which the horizontal axis is scaled by 307200/f eosc . third, an increase in the frequency of the external oscillator above 1mhz (a more than 3 increase in the output data rate) will start to decrease the effectiveness of the internal autocalibration circuits. this will result in a progressive v in /v ref (v) C0.5 inl (ppm of v ref ) 2 6 10 0.3 2482 f18 C2 C6 0 4 8 C4 C8 C10 C0.3 C0.1 0.1 0.5 v cc = 5v v ref = 5v v in(cm) = 2.5v t a = 25c c ref = 10f r = 1k r = 500 r = 100 figure 18. inl vs differential input voltage and reference source resistance for c ref > 1f ltc2482 26 2482fc applications information output data rate (readings/sec) C10 offset error (ppm of v ref ) 10 30 50 0 20 40 20 40 60 80 2482 f19 100 10 030507090 v in(cm) = v ref(cm) v cc = v ref = 5v v in = 0v f o = ext clock t a = 85c t a = 25c output data rate (readings/sec) 0 0 +fs error (ppm of v ref ) 500 1500 2000 2500 3500 10 50 70 2482 f20 1000 3000 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock t a = 85c t a = 25c figure 19. offset error vs output data rate and temperature figure 20. +fs error vs output data rate and temperature output data rate (readings/sec) 0 C3500 Cfs error (ppm of v ref ) C3000 C2000 C1500 C1000 0 10 50 70 2482 f21 C2500 C500 40 90 100 20 30 60 80 v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock t a = 85c t a = 25c output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 22 10 50 70 2482 f22 14 20 40 90 100 20 30 60 80 t a = 25c t a = 85c v in(cm) = v ref(cm) v cc = v ref = 5v f o = ext clock res = log 2 (v ref /inl max ) figure 21. Cfs error vs output data rate and temperature figure 22. resolution (inl max 1lsb) vs output data rate and temperature output data rate (readings/sec) 0 C10 offset error (ppm of v ref ) C5 5 10 20 10 50 70 2482 f23 0 15 40 90 100 20 30 60 80 v cc = 5v, v ref = 2.5v v cc = v ref = 5v v in(cm) = v ref(cm) v in = 0v f o = ext clock t a = 25c output data rate (readings/sec) 0 10 resolution (bits) 12 16 18 22 10 50 70 2482 f24 14 20 40 90 100 20 30 60 80 v cc = 5v, v ref = 2.5v v cc = v ref = 5v v in(cm) = v ref(cm) v in = 0v ref C = gnd f o = ext clock t a = 25c res = log 2 (v ref /inl max ) figure 23. offset error vs output data rate and reference voltage figure 24. resolution (inl max ) 2lsb vs output data rate and reference voltage ltc2482 27 2482fc applications information degradation in the converter accuracy and linearity. typical measured performance curves for output data rates up to 100 readings per second are shown in figures 19 to 24. in order to obtain the highest possible level of accuracy from this converter at output data rates above 20 readings per second, the user is advised to maximize the power supply voltage used and to limit the maximum ambient operating temperature. in certain circumstances, a reduction of the differential reference voltage may be bene? cial. input bandwidth the combined effect of the internal sinc 4 digital ? lter and of the analog and digital autocalibration circuits deter- mines the ltc2482 input bandwidth. when the internal oscillator is used the 3db input bandwidth is 3.3hz. if an external conversion clock generator of frequency f eosc is connected to the f o pin, the 3db input bandwidth is 10.7 ? 10 C6 ? f eosc . due to the complex ? ltering and calibration algorithms utilized, the converter input bandwidth is not modeled very accurately by a ? rst order ? lter with the pole located at the 3db frequency. when the internal oscillator is used, the shape of the ltc2482 input bandwidth is shown in figure 25. when an external oscillator of frequency f eosc is used, the shape of the ltc2482 input bandwidth can be derived from figure 25 in which the horizontal axis is scaled by f eosc /307200. the conversion noise (600nv rms typical for v ref = 5v) can be modeled by a white noise source connected to a noise free converter. the noise spectral density is 47nv hz for an in? nite bandwidth source and 64nv hz for a single 0.5mhz pole source. from these numbers, it is clear that particular attention must be given to the design of external ampli? cation circuits. such circuits face the simultaneous requirements of very low bandwidth (just a few hz) in order to reduce the output referred noise and relatively high bandwidth (at least 500khz) necessary to drive the input switched-capacitor network. a possible solution is a high gain, low bandwidth ampli? er stage followed by a high bandwidth unity-gain buffer. when external ampli? ers are driving the ltc2482, the adc input referred system noise calculation can be simpli? ed by figure 26. the noise of an ampli? er driving the ltc2482 input pin can be modeled as a band limited white noise source. its bandwidth can be approximated by the bandwidth of a single pole lowpass ? lter with a corner frequency f i . the ampli? er noise spectral density is n i . from figure 26, using f i as the x-axis selector, we can ? nd on the y-axis the noise equivalent bandwidth freq i of the input driving ampli? er. this bandwidth includes the band limiting effects of the adc internal calibration and ? ltering. the noise of the driving ampli? er referred to the converter input and including all these effects can be calculated as n = n i ? freq i . the total system noise differential input signal frequency (hz) 0 input signal attenuation (db) C3 C2 C1 0 4 2482 f25 C4 C5 C6 1 2 3 5 input noise source single pole equivalent bandwidth (hz) 1 input referred noise equivalent bandwidth (hz) 10 0.1 1 10 100 1k 10k 100k 1m 2482 f26 0.1 100 figure 25. input signal bandwidth using the internal oscillator figure 26. input referred noise equivalent bandwidth of an input connected white noise source ltc2482 28 2482fc applications information (referred to the ltc2482 input) can now be obtained by summing as square root of sum of squares the three adc input referred noise sources: the ltc2482 internal noise, the noise of the in+ driving ampli? er and the noise of the inC driving ampli? er. if the f o pin is driven by an external oscillator of frequency f eosc , figure 26 can still be used for noise calculation if the x-axis is scaled by f eosc /307200. for large values of the ratio f eosc /307200, the figure 26 plot accuracy begins to decrease, but at the same time the ltc2482 noise ? oor rises and the noise contribution of the driving ampli? ers lose signi? cance. normal mode rejection and antialiasing one of the advantages delta-sigma adcs offer over conventional adcs is on-chip digital ? ltering. combined with a large oversampling ratio, the ltc2482 signi? cantly simpli? es antialiasing ? lter requirements. additionally, the input current cancellation feature of the ltc2482 al- lows external lowpass ? ltering without degrading the dc performance of the device. the sinc 4 digital ? lter provides greater than 120db normal mode rejection at all frequencies except dc and integer multiples of the modulator sampling frequency (f s ). the ltc2482s autocalibration circuits further simplify the antialiasing requirements by additional normal mode signal ? ltering both in the analog and digital domain. independent of the operating mode, f s = 256 ? f n = 2048 ? f outmax where f n is the notch frequency and f outmax is the maximum output data rate. in the internal oscilla- tor mode with 50hz/60hz rejection, f s = 13960hz. in the external oscillator mode, f s = f eosc /20. the regions of low rejection occurring at integer multiples of f s have a very narrow bandwidth. magni? ed details of the normal mode rejection curves are shown in figure 27 (rejection near dc) and figure 28 (rejection at f s = 256f n ) where f n represents the notch frequency. these curves have been derived for the external oscillator mode but they can be used in all operating modes by appropriately selecting the f n value. the user can expect to achieve this level of performance using the internal oscillator as it is demonstrated by figure 29. typical measured values of the normal mode rejection of the ltc2482 operating with an internal oscil- lator (50hz/60hz rejection) is shown in figure 29. as a result of these remarkable normal mode speci? ca- tions, minimal (if any) antialias ? ltering is required in front of the ltc2482. if passive rc components are placed in front of the ltc2482, the input dynamic current should be considered (see input current section). in this case, the differential input current cancellation feature of the ltc2482 allows external rc networks without signi? cant degradation in dc performance. traditional high order delta-sigma modulators, while providing very good linearity and resolution, suffer from potential instabilities at large input signal levels. the proprietary architecture used for the ltc2482 third input signal frequency (hz) input normal mode rejection (db) 2482 f27 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 f n 0 2f n 3f n 4f n 5f n 6f n 7f n 8f n f n = f eosc /5120 input signal frequency (hz) 250f n 252f n 254f n 256f n 258f n 260f n 262f n input normal mode rejection (db) 2482 f28 0 C10 C20 C30 C40 C50 C60 C70 C80 C90 C100 C110 C120 figure 27. input normal mode rejection at dc figure 28. input normal mode rejection at f s = 256f n ltc2482 29 2482fc order modulator resolves this problem and guarantees a predictable stable behavior at input signal levels of up to 150% of full scale. in many industrial applications, it is not uncommon to have to measure microvolt level signals superimposed over volt level perturbations and the ltc2482 is eminently suited for such tasks. when the perturbation is differential, the speci? cation of interest is the normal mode rejection for large input signal levels. with a reference voltage v ref = 5v, the ltc2482 has a full-scale differential input range of 5v peak-to-peak. remote sensing with easy drive input current cancellation one problem faced by designers of high performance data acquisition systems is achieving data sheet speci? ed per- formance in a real world environment. one advantage delta sigma type adcs offer over the alternatives is on-chip digital ? ltering (noise suppression). the disadvantage (solved by easy drive technology) is the drive requirements inherent in delta sigma adc architectures. in order to demonstrate the full potential of the easy drive technology, a practical test case was characterized (see figure 30). precise measurements of offset, noise and linearity were measured under extreme test conditions. a remote sensor was digitized through 100 meters of cable applied to an rc network with low accuracy 1% resistors. a remote sen- sor voltage was swept from 0 to 2.5 with less than 1lsb linearity error (see figure 31). noise levels of 650nv rms and offsets below 5v were measured (see figure 32). fundamentally, an oversampled data converter ( ? adc) directly connected to a long cable and a low precision rc network leads to many problems greatly limiting the accuracy of the system. these include transmission line effects, noise and dc settling errors. the sampling network of ? adcs injects high frequency current spikes into the cable. the resulting voltage spikes are re? ected through the long wire and result in excessive noise and reduced accuracy. this problem is solved by placing a bypass capacitor across the input to the adc. this capacitor serves as a charge reservoir for the adcs sampling network and reduces the voltage spikes by the ratio of internal sampling capacitor to external bypass capacitor. a 1f bypass capacitor reduces the voltage spikes generated by the sampling network by a factor of 50,000 (1v spikes are reduced to 18v) and is suf? cient to achieve data sheet speci? ed noise and accuracy. the addition the large external bypass capacitor results in input settling errors. typical 24-bit high resolution delta sigma adcs sample at time intervals on the order of 10s. in order to fully settle with a 1f bypass capacitor, the source impedance must be lower than 1. source impedances greater than 1 result in offset and full-scale errors due to the accumulation of charge settling errors over the complete conversion cycle. easy drive technology automatically removes the differential component of this error. the remaining common mode error is reduced to a ? xed offset as a function of the external resistor match- ing seen at the plus and minus input of the adc. in this extreme case, 1k external resistors with 1% matching result in a 3.5v offset while the linearity and noise are unaffected. the signal path contains a 100 meter wire connected to a low voltage source in a very noisy environment. line frequency noise is rejected by the on-chip digital ? lter and guaranteed by the high accuracy on-chip oscillator. high frequency noise is rejected by the external lowpass ? lter formed by the input bypass capacitor and external resistors. applications information input frequency (hz) 0 20 40 60 80 100 120 140 160 180 200 220 normal mode rejection (db) 2482 f29 0 C20 C40 C60 C80 C100 C120 v cc = 5v v ref = 5v v in(cm) = 2.5v v in(p-p) = 5v t a = 25c measured data calculated data figure 29. input normal mode rejection vs input frequency with input perturbation of 100% full scale ltc2482 30 2482fc package description dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699) 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.38 0.10 bottom view?xposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ?0.05 (dd) dfn 1103 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.675 0.05 3.50 0.05 package outline 0.25 0.05 0.50 bsc ltc2482 31 2482fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number c 7/10 revised typical application drawing added note 16 1, 32 4, 5 (revision history begins at rev c) ltc2482 32 2482fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2005 lt 0710 rev c ? printed in usa related parts typical application 100 meters cs sck sdo f o v cc 5v ltc2482 ref gnd c7 0.1f c8 1f 0.1f 0.1f 1k 1% 2482 f30 gnd 1k 1% remote sensor v in + v in C 1f figure 30. differential input current cancellation enables direct digitization of remote sensors input voltage (v) 0 inl (lsb) 5 4 3 2 1 0 C1 C2 C3 C4 C5 2 2482 f31 0.5 1 1.5 2.5 integral nonlinearity through 100 meters of wire and a 1k, 1f rc network output reading (mv) C5.25 number of readings (%) 8 10 12 C3.45 C2.25 2482 f32 6 4 C4.65 C4.05 C2.85 C1.65 2 0 rms noise = 630nv average = C3.5v 2500 consecutive readings figure 31. current cancellation enables precise dc measurements under extreme conditions figure 32. input current cancellation enables low noise/ low offset measurements under extreme conditions part number description comments ltc1050 precision chopper stabilized op amp no external components 5v offset, 1.6v p-p noise lt1236a-5 precision bandgap reference, 5v 0.05% max initial accuracy, 5ppm/c drift lt1460 micropower series reference 0.075% max initial accuracy, 10ppm/c max drift ltc2400 24-bit, no latency ? adc in so-8 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200a ltc2401/ltc2402 1-/2-channel, 24-bit, no latency ? adcs in msop 0.6ppm noise, 4ppm inl, 10ppm total unadjusted error, 200a ltc2404/ltc2408 4-/8-channel, 24-bit, no latency ? adcs with differential inputs 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200a ltc2410 24-bit, no latency ? adc with differential inputs 0.8v rms noise, 2ppm inl ltc2411/ltc2411-1 24-bit, no latency ? adcs with differential inputs in msop 1.45v rms noise, 4ppm inl, simultaneous 50hz/60hz rejection (ltc2411-1) ltc2413 24-bit, no latency ? adc with differential inputs simultaneous 50hz/60hz rejection, 800nv rms noise ltc2415/ ltc2415-1 24-bit, no latency ? adcs with 15hz output rate pin compatible with the ltc2410 ltc2414/ltc2418 8-/16-channel 24-bit, no latency ? adcs 0.2ppm noise, 2ppm inl, 3ppm total unadjusted errors 200a ltc2420 20-bit, no latency ? adc in so-8 1.2ppm noise, 8ppm inl, pin compatible with ltc2400 ltc2430/ltc2431 20-bit, no latency ? adcs with differential inputs 2.8v noise, ssop-16/msop package ltc2435/ltc2435-1 20-bit, no latency ? adcs with 15hz output rate 3ppm inl, simultaneous 50hz/60hz rejection ltc2440 high speed, low noise 24-bit ? adc 3.5khz output rate, 200mv noise, 24.6 enobs ltc2480 16-bit, no latency ? adc with pga and temperature sensor pin compatible with ltc2482 ltc2484 24-bit, no latency ? adc with temperature sensor pin compatible with ltc2482 |
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